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| integrated silicon solution, inc. 1 rev. c 07/20/11 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to mak e changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat- est version of this device specifcation before relying on any published information and before placing orders for products. is42s32160c august 2011 features: ? clock frequency: 166, 133 mhz ? fully synchronous operation ? inter nal pipelined architecture ? progr ammable mode C cas# latency: 2 or 3 C burst length: 1, 2, 4, 8, or full page C burst type: interleav ed or linear ? po wer supply v d d /v d d q +3.3v 0.3v ? lvttl interface ? a uto refresh and self refresh ? individual byte controlled by dqm0-3 options: ? die revision: c ? confguration(s): 16mx32 ? pac kage(s): 90 ball bga (8x13mm) ? lead-free package availab le ? temperature range: commercial and industrial 16mx32 512mb synchronous dram description: the issi's is42s32160c is a 512mb synchronous dram confgured as a quad 4m x32 dram. it achieves high-speed data transfer using a pipeline architecture with a synchronous interface . all inputs and outputs sig- nals are registered on the rising edge of the clock input, clk. the 512mb sdram is internally confgured by stacking two 256mb, 16mx16 devices. each of the 4m x32 banks is organized as 8192 rows by 512 columns by 32 bits. key timing parameters p arameter -6 -75 unit clk cycle time cas latency = 2 10 10 ns cas latency = 3 6.0 7.5 ns clk frequency cas latency = 2 100 100 mhz cas latency = 3 166 133 mhz access time from clock cas latency = 2 6.5 6.5 ns cas latency = 3 5.4 6 ns address table parameter 16mx32 confguration 4m x 32 x 4 banks bank address pins ba0, ba1 autoprecharge pins a10/ap row addresses a0 C a12 column addresses a0 C a8 refresh count 8192 / 64ms
2 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c die 01 die 02 dq0 ?dq31 cs clk cke# command addresses clk cke cs ras cas we a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba0 ba1 a10 a12 command decoder & clock generator mode register refresh controller refresh counter self refresh controller row address latch multiplexer column address latch burst counter column address buffer column decoder data i n buffer data out buffer dqml dqmh dq 0-15 v dd /v ddq v ss /v ss q 13 13 9 13 13 9 16 16 16 16 512 (x 16) 8192 8192 8192 row decoder 8192 memory cell array bank 0 sense amp i/o gate bank control logic row address buffer a11 2 functional block diagram 16mbx16 sdram functional block diagram 16mbx32 sdram integrated silicon solution, inc. ? 1-800-379-4774 3 rev. c 07/20/11 is42s32160 c 1 pin descriptions symbol type description clk input clock: clk is driven by the system clock.all sdram input signals are sampled on the positive edge of clk.clk also increments the internal burst counter and controls the output registers. cke input clock enable: cke activates(high)and deactivates(low) the clk signal.if cke goes low syn- chronously with clock(set-up and hold time same as other inputs),the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low.when all banks are in the idle state,deactivating the clock controls the entry to the power down and self refresh modes.cke is synchronous except after the device enters power down and self refresh modes,where cke becomes asynchronous until exiting the same mode. the input buffers,including clk,are disabled during power down and self refresh modes,providing low standby power. bs0,bs1 input bank select:bs0 and bs1 defines to which bank the bankactivate,read,write,or bankprecharge command is being applied. a0-a12 input address inputs: a0-a12 are sampled during the bankactivate command (row address a0-a12) and read/write command (column address a0-a8 with a10 defining auto precharge) to select one location in the respective bank.during a precharge command,a10 is sampled to determine if all banks are to be precharged (a10 =high). the address inputs also provide the op-code during a mode register set . cs# input chip select: cs# enables (sampled low) and disables (sampled high) the command decoder.all commands are masked when cs# is sampled high.cs#provides for external bank selection on systems with multiple banks.it is considered part of the command code. ras# input row address strobe: the ras# signal defines the operation commands in conjunction with the cas# and we# signals and is latched at the positive edges of clk.when ras# and cs# are as- serted ?low?and cas# is asserted ?high,?either the bankactivate command or the precharge command is selected by the we#signal.when the we#is asserted ?high,?the bankactivate com- mand is selected and the bank designated by bs is turned on to the active state.when the we# is asserted ?low,?the precharge command is selected and the bank designated by bs is switched to the idle state after the precharge operation. cas# input column address strobe: the cas# signal defines the operation commands in conjunction with the ras# and we# signals and is latched at the positive edges of clk. when ras# is held ?high?and cs#is asserted ?low,?the column access is started by asserting cas#?low.?then, the read or write command is selected by asserting we# ?low?or ?high.? we# input write enable: the we# signal defines the operation commands in conjunction with the ras# and cas# signals and is latched at the positive edges of clk.the we# input is used to select the bankactivate or precharge command and read or write command. dqm0-3 input input data input/output mask: dqm0-dqm3 are byte specific, nonpersistent i/o buffer controls. the i/o buffers are placed in a high-z state when dqm is sampled high.input data is masked when dqm is sampled high during a write cycle.output data is masked (two-clock latency) when dqm is sampled high during a read cycle. dqm3 masks dq31-dq24, dqm2 masks dq23-dq16, dqm1 masks dq15-dq8, and dqm0 masks dq7-dq0. dq0-31 / output data i/o: the dq0-31 input and output data are synchronized with the positive edge of clk. the i/os are byte-maskable during reads and writes. 4 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c pin configuration package code: b 90 ball fbga (top view) (8.00 mm x 13.00 mm body, 0.8 mm ball pitch) 1 2 3 4 5 6 7 8 9 a b c d e f g h j k l m n p r dq26 dq28 vssq vssq vddq vss a4 a7 clk dqm1 vddq vssq vssq dq11 dq13 dq24 vddq dq27 dq29 dq31 dqm3 a5 a8 cke nc dq8 dq10 dq12 vddq dq15 vss vssq dq25 dq30 nc a3 a6 a12 a9 nc vss dq9 dq14 vssq vss vdd vddq dq22 dq17 nc a2 a10 nc ba0 cas vdd dq6 dq1 vddq vdd dq23 vssq dq20 dq18 dq16 dqm2 a0 ba1 cs we dq7 dq5 dq3 vssq dq0 dq21 dq19 vddq vddq vssq vdd a1 a11 ras dqm0 vssq vddq vddq dq4 dq2 pin descriptions a0-a12 row address input a0-a8 column address input ba0, ba1 bank select address dq0 to dq31 data i/o clk system clock input cke clock enable cs chip select ras row address strobe command cas column address strobe command we write enable dqm0-dqm3 x32 input/output mask v dd power vss ground v ddq power supply for i/o pin vss q ground for i/o pin nc no connection integrated silicon solution, inc. ? 1-800-379-4774 5 rev. c 07/20/11 is42s32160 c command state cken-1 cke dqm (6) bs0,1 a10 a9-0 a12, a11 cs# ras# cas# we# bankactivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) hxxvl lhll write and auto precharge active (3) hxxvh lhll read active (3) hxxvl lhlh read and autoprecharge active (3) hxxvh lhlh mode register set idle h x x op code l l l l no-operation any h x x x x x l h h h burst stop active (4) hxxxxx lhhl device deselect any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x (selfrefresh) l h h h clock suspend mode entry active h l x x x x x x x x power down mode entry any (5) hlxxxx hxxx lh h h clock suspend mode exit active l h x x x x x x x x power down mode exit any l h x x x x h x x x (powerdown) l h h h data write/output enable active h x l x x x x x x x data mask/output disable active h x h x x x x x x x column address (a0 ~a8) column address (a0 ~a8) operation mode fully synchronous operations are performed to latch the commands at the positive edges of clk. truth table shows the operation commands. note: 1. v =valid,x =don ?t care,l =logic low,h =logic high 2. cken signal is input level when commands are provided. cken-1 signal is input level one clock cycle before the commands are provided. 3. these are states of bank designated by bs signal. 4. device state is 1,2,4,8,and full page burst operation. 5. power down mode can not enter in the burst operation. when this command is asserted in the burst cycle,device state is clock suspend mode. 6. dqm0-3 truth table (1),(2) 6 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c i ? i commands 1 bankactivate (ras#=?l?, cas#=?h?, we#=?h?, bs =bank, a0-a12 =row address) the bankactivate command activates the idle bank designated by the bs0,1 (bank select) signal.by latching the row address on a0 to a12 at the time of this command, the selected row access is initiated.the read or write operation in the same bank can occur after a time delay of trcd(min.) from the time of bank activation.a subsequent bankactivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure).the minimum time interval between successive bankactivate commands to the same bank is defined by trc(min.).the sdram has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area;therefore it restricts the back-to-back activation of the four banks. trrd(min.) specifies the minimum time required between activating different banks. after this command is used,the write command and the block write command perform the no mask write operation. clk address t0 t1 t2 t3 tn+3 tn+4 tn+5 tn+6 .............. command .............. .............. nop nop nop nop ras# - cas# delay ( t rcd ) ras#- ras# delay time ( t rrd ) ras# cycle time ( t rc ) bank a row addr. bank a col addr. bank b row addr. bank a row addr. bank a activate r/w a with autoprecharge bank b activate bank a activate auto precharge begin :"h" or "l" bank activate 2 bankprecharge command (ras#=?l?, cas#=?h?, we#=?l?, bs =bank, a10 =?l?) the bankprecharge command precharges the bank disignated by bs0,1 signal.the precharged bank is switched from the active state to the idle state.this command can be asserted anytime after tras(min.) is satisfied from the bankactivate command in the desired bank.the maximum time any bank can be active is specified by tras(max.).therefore,the precharge function must be performed in any active bank within tras(max.).at the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. integrated silicon solution, inc. ? 1-800-379-4774 7 rev. c 07/20/11 is42s32160c 3 prechargeall command (ras#=?l?, cas#=?h?, we#=?l?, bs =don t care, a10 =?h?) the precharge all command precharges all the four banks simultaneously and can be issued even if all banks are not in the active state. all banks are then switched to the idle state. 4 read command (ras#=?h?, cas#=?l?, we#=?h?, bs =bank, a10 =?l?, a0-a8 =column address) the read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank.the bank must be active for at least trcd(min.) before the read command is issued.during read bursts, the valid data-out element from the starting column address will be available following the cas# latency after the issue of the read command.each subsequent data- out element will be valid by the next positive clock edge (refer to the following figure).the dqs go into high-impedance at the end of the burst unless other command is initiated. the burst length,burst sequence,and cas# latency are determined by the mode register which is already programmed. a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). t0 t2 t1 t3 t4 t5 t6 t7 t8 read a nop nop nop nop nop nop nop nop dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 clk command cas# latency=2 t ck2 , dq- s cas# latency=3 t ck3 , dq- s burst read operation(burst length =4,cas#latency =2,3) the read data appears on the dqs subject to the values on the dqm inputs two clocks earlier (i.e.dqm latency is two clocks for output buffers). a read burst without the auto precharge function may be interrupted by a subsequent read or write command to the same bank or the other active bank before the end of the burst length.it may be interrupted by a bankprecharge/prechargeall command to the same bank too.the interrupt coming from the read command can occur on any clock cycle following a previous read command (refer to the following figure). 8 integrated silicon solution, inc. rev. c 07/20/11 is42s32160 c read a read b nop nop nop nop nop nop nop dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 3 2 dout b clk command cas# latency=2 t ck2 , dq- s cas# latency=3 t ck3 , dq- s t0 t2 t1 t3 t4 t5 t6 t7 t8 read interrupted by a read (burst length =4,cas#latency =2,3) the dqm inputs are used to avoid i/o contention on the dq pins when the interrupt comes from a write command.the dqms must be asserted (high)at least two clocks prior to the write command to suppress data-out on the dq pins.to guarantee the dq pins against i/o contention,a single cycle with high-impedance on the dq pins must occur between the last read data and the write command (refer to the following three figures).if the data output of the burst read occurs at the second clock of the burst write,the dqms must be asserted (high)at least one clock prior to the write command to avoid internal bus contention. integrated silicon solution, inc. ? 1-800-379-4774 9 rev. c 07/20/11 is42s32160c read a nop nop nop nop write b nop nop dqm command dq?s nop dout a dinb 2 dinb 1 dinb 0 must be hi-z before the write com mand : "h" or "l" clk t0 t2 t1 t3 t4 t5 t6 t7 t8 clk dqm command nop nop nop nop nop banka activat e din a 0 din a 1 din a 2 din a 3 1 clk interval cas# latency=2 read a writea : "h" or "l" nop t0 t2 t1 t3 t4 t5 t6 t7 t8 tck2, dqs clk dqm command nop read a nop nop nop nop din b 0 din b 1 din b 2 din b 3 cas# latency=2 nop nop : "h" or "l" t ck2 , dq?s t0 t2 t1 t3 t4 t5 t6 t7 t8 writeb tck2, dqs read to write interval (burst length = 4,cas# latency =3) read to write interval (burst length = 4,cas# latency =2) read to write interval (burst length = 4,cas# latency =2) a read burst without the auto precharge function may be interrupted by a bankprecharge/ prechargeall command to the same bank.the figure "read to precharge" shows the optimum time that bankprecharge/prechargeall command is issued in different cas# latency. 10 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c i ? b read to precharge (cas#latency =2,3) 5 write command (ras#=?h?, cas#=?l?, we#=?l?, bs =bank, a10 =?l?, a0-a8 =column address) the write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank.the bank must be active for at least trcd(min.) before the write command is issued.during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge (refer to figure "burst write operation").the dqs remain with high- impedance at the end of the burst unless another command is initiated.the burst length and burst sequence are determined by the mode register,which is already programmed. a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). clk command read a nop nop nop nop activate nop nop precharge dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 address t rp bank, col a bank(s) cas# latency=2 t ck2 , dq's cas# latency=3 t ck3 , dq's t0 t2 t1 t3 t4 t5 t6 t7 t8 bank, row clk command din a 3 nop writea i nop nop nop nop nop nop nop din a 0 din a 1 din a 2 dq0 - dq3 the first data element and the write are registered on the same clock edge. extra data is masked. don?t care t0 t2 t1 t3 t4 t5 t6 t7 t8 burst write operation (burst length =4,cas# latency =2,3) a write burst without the autoprecharge function may be interrupted by a subsequent write, bankprecharge/ prechargeall,or read command before the end of the burst length. an interrupt coming from write command can occur on any clock cycle following the previous write command (refer to the figure "write interrupted by a write"). integrated silicon solution, inc. ? 1-800-379-4774 11 rev. c 07/20/11 is42s32160c clk command din b 2 nop writea writeb nop nop nop nop nop nop din a 0 din b 0 din b 1 dq?s din b 3 1 clk interval t0 t2 t1 t3 t4 t5 t6 t7 t8 clk command t 0t 1 t 2t 3 t 4t 5 t 6t 7 t 8 nop writea nop nop nop nop nop read b nop din a 0 don?t care dout b 2 dout b 0 dout b 1 dout b 3 din a 0 don?t care don?t care dout b 2 dout b 0 dout b 1 dout b 3 di n input data must be removed from the dqs at least one clock cycle before the read data appears on the outputs to avoid data contention. input data for the write is masked. cas# latency=2 t ck2 , dq?s cas# latency=3 t ck3 , dq?s clk write command bank (s) row nop nop precharge nop nop activate bank col n din din nn + 1 dqm address dq t wr t rp : don't care t0 t2 t1 t3 t4 t5 t6 write interrupted by a write (burst length =4, cas# latency =2,3) the read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. in order to avoid data contention, input data must be removed from the dqs at least one clock cycle before the first read data appears on the outputs (refer to figure "write interrupted by a read". once the read command is registered, the data inputs will be ignored and writes will not be executed. write interrupted by a read (burst length =4, cas# latency =2,3) the bankprecharge/prechargeall command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered,where m equals twr/ tck rounded up to the next whole number. in addition, the dqm signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the bankprecharge/ prechargeall command is entered (refer to the figure "write to precharge"). note: the dqms can remain low in this example if the length of the write burst is 1 or 2. write to precharge 10 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c i ? b read to precharge (cas#latency =2,3) 5 write command (ras#=?h?, cas#=?l?, we#=?l?, bs =bank, a10 =?l?, a0-a8 =column address) the write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank.the bank must be active for at least trcd(min.) before the write command is issued.during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge (refer to figure "burst write operation").the dqs remain with high- impedance at the end of the burst unless another command is initiated.the burst length and burst sequence are determined by the mode register,which is already programmed. a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). clk command read a nop nop nop nop activate nop nop precharge dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 address t rp bank, col a bank(s) cas# latency=2 t ck2 , dq's cas# latency=3 t ck3 , dq's t0 t2 t1 t3 t4 t5 t6 t7 t8 bank, row clk command din a 3 nop writea i nop nop nop nop nop nop nop din a 0 din a 1 din a 2 dq0 - dq3 the first data element and the write are registered on the same clock edge. extra data is masked. don?t care t0 t2 t1 t3 t4 t5 t6 t7 t8 burst write operation (burst length =4,cas# latency =2,3) a write burst without the autoprecharge function may be interrupted by a subsequent write, bankprecharge/ prechargeall,or read command before the end of the burst length. an interrupt coming from write command can occur on any clock cycle following the previous write command (refer to the figure "write interrupted by a write"). integrated silicon solution, inc. ? 1-800-379-4774 13 rev. c 07/20/11 is42s32160c i ? i (iii) write with auto precharge interrupted by a read interrupted by a read (with or without auto precharge): a read to bank m will interrupt a write on bank n when registered, with the data-out ap- pearing cas latency later. the precharge to bank n will begin after twr is met, where twr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m. write with auto precharge interrupted by a read (iv) write with auto precharge interrupted by a write interrupted by a write (with or without auto precharge): a write to bank m will interrupt a write on bank n when when registered. the precharge to bank n will begin after twr is met, where twr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m. write with auto precharge interrupted by a write d in a d in d + 2 d in d + 3 don?t care t2 t1 t4 t3 t6 t5 t0 command t7 bank n nop d in d + 1 write - ap bank n nop nop nop note: 1. dqm is low. bank n, col a bank m, col d write - ap bank m nop d in a + 1 d in a + 2 d in d page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m bank m address internal states t page active write with burst of 4 interrupt burst, write-back precharge t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop note: 1. dqm is low. bank n, col a bank m, col d read - ap bank m nop nop page active read with burst of 4 internal states t page active write with burst of 4 interrupt burst, write-back precharge wr - bank n rp - bank n t t rp - bank m t7 bank n bank m address clk dq d in a d in a + 1 d out d d out d + 1 cas latency = 3 (bank m) don?t care 14 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c 7 mode register set command (ras# =?l?, cas# =?l?, we# =?l?, bs0,1 and a12-a0 =register data) the mode register stores the data for controlling the various operating modes of sdram. the mode register set command programs the values of cas# latency, addressing mode and burst length in the mode register to make sdram useful for a variety of different applications. the default values of the mode register after power-up are undefined;therefore this command must be issued at the power-up sequence.the state of pins bs0,1 and a0-a12 in the same cycle is the data written to the mode register.one clock cycle is required to complete the write in the mode register (refer to figure "mode register set cycle").the contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state. ras# clk cke cs# cas# we# addr. dqm dq t ck2 clock min. address key t rp hi-z precharge all mode register set command any command t0 t2 t1 t3 t4 t5 t6 t7 t8 t9 t10 mode register set cycle integrated silicon solution, inc. ? 1-800-379-4774 15 rev. c 07/20/11 is42s32160c i ? i m the mode register is divided into various fields depending on functionality. *note:rfu (reserved for future use)should stay 0 during mrs cycle. burst length field (a2~a0) this field specifies the data length of column access using the a2~a0 pins and selects the burst length to be 2, 4, 8, or full page. a2 a1 a0 burst length 0001 0012 0104 0118 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 full page address bs0,1 a1 2-a1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function rfu* wbl test mode cas latency bt burst length data n 0 1234567 -255256257 - column address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 - 2 words: burst length 4 words: 8 words: full page: column address is repeated until terminated. burst type field (a3) the burst type can be one of two modes,interleave mode or sequential mode. ? addressing sequence of sequential mode an internal column address is performed by increasing the address from the column address which is input to the device.the internal column address is varied by the burst length as shown in the following table. when the value of column address,(n +m),in the table is larger than 255, only the least significant 8 bits are effective. a3 burst type 0 sequential 1 interleave 16 integrated silicon solution, inc. rev. c 07/20/11 is42s32160 c ? addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. cas# latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read command to the first read data.the minimum whole value of cas# latency depends on the frequency of clk.the minimum whole value satisfying the following formula must be programmed into this field. t cac (min)<=cas# latency x t ck a6 a5 a4 cas#latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 x x reserved data n column address burst leng t h data 0 a7 a6 a5 a4 a3 a2 a1 a0 data 1 a7 a6 a5 a4 a3 a2 a1 a0 #4 words data 2 a7 a6 a5 a4 a3 a2 a1# a0 data 3 a7 a6 a5 a4 a3 a2 a1# a0 # 8 words data 4 a7 a6 a5 a4 a3 a2# a1 a0 data 5 a7 a6 a5 a4 a3 a2# a1 a0 # data 6 a7 a6 a5 a4 a3 a2# a1# a0 data 7 a7 a8 a8 a8 a8 a8 a8 a8 a8 a6 a5 a4 a3 a2# a1# a0 # integrated silicon solution, inc. ? 1-800-379-4774 17 rev. c 07/20/11 is42s32160c i ? i test mode field (a8~a7) these two bits are used to enter the test mode and must be programmed to ?00?in normal operation. write burst length (a9) this bit is used to select the burst write length. 8 no-operation command (ras# =?h?, cas# =?h?, we# =?h?) the no-operation command is used to perform a nop to the sdram which is selected (cs# is low).this prevents unwanted commands from being registered during idle or wait states. 9 burst stop command (ras# =?h?, cas# =?h?, we# =?l?) the burst stop command is used to terminate either fixed-length or full-page bursts.this command is only effective in a read/write burst without the auto precharge function.the terminated read burst ends after a delay equal to the cas# latency (refer to figure "termination of a burst read operation"). the termination of a write burst is shown in the figure "termination of a burst write operation". termination of a burst read operation (burst length > 4 , cas# latency =2,3) termination of a burst write operation (burst length =x) clk command t 0t 1t 2t 3 t 4t 5 t 6t 7 t 8 read a nop nop nop nop nop nop nop cas# latency = 2 tck2,dq?s dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 cas# latency = 3 tck3,dq?s the burst ends after a delay equal to the cas# latency. burst stop cl k comman d t 0t 1t 2t 3t 4t 5t 6t 7t 8 nop write a nop nop nop nop nop nop burst stop cas# latency=2,3 dq?s din a 0 din a 1 din a 2 don?t care input data for the write is masked. a8 a7 test mode 0 0 normal mode 0 1 vendor use only 1 x vendor use only a9 write burst length 0 burst 1 single bit 18 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c 10 device deselect command (cs# =?h?) the device deselect command disables the command decoder so that the ras#,cas#,we# and address inputs are ignored,regardless of whether the clk is enabled.this command is similar to the no operation command. 11 autorefresh command (ras# =?l?, cas# =?l?, we# =?h?, cke =?h?) the autorefresh command is used during normal operation of the sdram and is analogous to cas#-before- ras#(cbr)refresh in conventional drams.this command is non-persistent, so it must be issued each time a refresh is required.the addressing is generated by the internal refresh controller.this makes the address bits a ?don?t care?during an autorefresh command.the internal refresh counter increments automatically on every auto refresh cycle to all of the rows.the refresh operation must be performed 8192 times within 64ms. the time required to complete the auto refresh operation is specified by trc(min.).to provide the autorefresh command, all banks need to be in the idle state and the device must not be in power down mode (cke is high in the previous cycle).this command must be followed by nops until the auto refresh operation is completed.the precharge time requirement,trp(min),must be met before successive auto refresh operations are performed. 12 selfrefresh entry command (ras# =?l?, cas# =?l?, we# =?h?, cke =?l?) the selfrefresh is another refresh mode available in the sdram. it is the preferred refresh mode for data retention and low power operation.once the selfrefresh command is registered, all the inputs to the sdram become ?don't care?with the exception of cke, which must remain low.the refresh addressing and timing is internally generated to reduce power consumption.the sdram may remain in selfrefresh mode for an indefinite period. the selfrefresh mode is exited by restarting the external clock and then asserting high on cke (selfrefresh exit command). 13 selfrefresh exit command (cke =?h?, cs# =?h?or cke =?h?, ras# =?h?,cas# =?h?, we# =?h?) this command is used to exit from the selfrefresh mode. once this command is registered, nop or device deselect commands must be issued for trc(min.) because time is required for the completion of any bank currently being internally refreshed. if auto refresh cycles in bursts are performed during normal operation, a burst of 8192 auto refresh cycles should be completed just prior to entering and just after exiting the selfrefresh mode. 14 clock suspend mode entry /powerdown mode entry command (cke =?l?) when the sdram is operating the burst cycle, the internal clk is suspended(masked)from the subsequent cycle by issuing this command (asserting cke ?low?). the device operation is held intact while clk is suspended.on the other hand,when all banks are in the idle state,this command performs entry into the powerdown mode.all input and output buffers (except the cke buffer) are turned off in the powerdown mode. the device may not remain in the clock suspend or powerdown state longer than the refresh period (64ms) since the command does not perform any refresh operations. 15 clock suspend mode exit /powerdown mode exit command when the internal clk has been suspended, the operation of the internal clk is initiated from the subsequent cycle by providing this command (asserting cke ?high?). when the device is in the powerdown mode, the device exits this mode and all disabled buffers are turned on to the active state. t pde (min.) is required when the device exits from the powerdown mode. any subsequent commands can be issued after one clock cycle from the end of this command. 16 data write /output enable,data mask /output disable command (dqm =?l?,?h?) during a write cycle, the dqm signal functions as a data mask and can control every word of the input data.during a read cycle, the dqm functions as the controller of output buffers. dqm is also used for device selection, byte selection and bus control in a memory system. integrated silicon solution, inc. ? 1-800-379-4774 19 rev. c 07/20/11 is42s32160c i ? i absolute maximum ratings (1) dc recommended operating conditions symbol parameter min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v v ddq supply voltage for dq 3.0 3.3 3.6 v v ih high level input voltage (all inputs) 2.0 ? v dd + 0.3 v v il low level input voltage (all inputs) - 0.3 ? +0. 8 v notes: 1. all voltages are referenced to v ss =0v 2. vih(overshoot): vih (max) = vdd + 2v (pulse width 3ns) 3. vil(undershoot): vil (min) = - 2v (pulse width 3ns) capacitance characteristics (at t a = 0 ~ 70c, v dd = v ddq = 3.3 0.3v, v ss = v ssq = 0v , unless otherwise note d ) symbol parameter min. max. unit c in input capacitance, address & control pin 5.0 7.0 pf c clk i nput capacitance, clk pin 5.0 7.6 pf c i / o data input/output capacitance 8 12 pf symbol parameters rating unit v dd supply voltage (with respect to v ss ) ?0.5 to +4.6 v v ddq supply voltage for output (with respect to v ssq ) ?0.5 to +4.6 v v i input voltage (with respect to v ss ) ?0.5 to v dd +0.5 v v o output voltage (with respect to v ssq ) ?1.0 to v ddq +0.5 v i cs short circuit output current 50 ma p d power dissipation ( t a = 25 c) 1w t opt operating temperature com. 0 to +70 c ind. -40 to +85 t stg storage temperature ?5 5 to +150 c notes: 1. exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to abso lute maximum rating conditions for extended periods may affect device reliability. 20 integrated silicon solution, inc. rev. c 07/20/11 is42s32160 c symbol unit note operating current t rc 3 t rc (min), outputs open, input signal one transition per one cycle 1 bank operation i dd1 3 precharge standby current in power down mode precharge standby current in non-power down mode precharge standby current in non-power down mode t ck = 15ns, cke v il (max) i dd2p i dd2n i dd2ns precharge standby current in power down mode t ck = , cke v il (max) i dd2ps -75 -6 max. 270 300 4 4 4 4 60 40 40 60 parameter description min. max. unit note i il input leakage current (0v v in v dd , all other pins not under test = 0v ) - 5 + 5 m a i ol 2.4 v v oh lvttl output "h" level voltage ( i out = -2ma ) v ol lvttl output "l" level voltage ( i out = 2ma ) 0.4 v output leakage current (0v v out v dd , dq disable ) - 5 + 5 ma d.c. electrical characteristics (recommended operating conditions) cke v ih (min), cs# 3 v ih (min), t ck = 15ns cke 3 v ih (min), clk v il (max), t ck = active standby current in power down mode c ke v il (max), t ck = 15ns i dd3p active standby current in power down mode cke& clk v il (max), t ck = i dd3ps active standby current in non-power down mode cke v ih (min), cs# 3 v ih (min), t ck = 15ns i dd3n active standby current in non-power down mode cke 3 3 v ih (min), clk v il (max), t ck = i dd3ns operating current (burst mode) t ck =t ck (min), outputs open, multi-bank interleave i dd4 3, 4 refresh current t rc 3 t rc (min) i dd5 3 self refresh current c ke 0.2v i dd6 1 6 6 80 50 260 320 6 6 6 80 50 300 360 6 ma description/ test condition integrated silicon solution, inc. ? 1-800-379-4774 21 rev. c 07/20/11 is42s32160 c - 75 - 6 symbol a.c. parameter min. max. max. min. unit note t rc row cycle time (same bank) 9 t rrd row activate to row activate delay (different banks) 9 t rcd ras# to cas# delay (same bank) 9 t rp precharge to refresh/row activate command (same bank) 9 t ras row activate to precharge time (same bank) 9 t ck2 clock cycle time cl* = cl* = 2 cl* = 3 2 t ck3 cl* = 3 ns access time from clk 9 t ac2 t ac3 (positive edge) t oh data output hold time 9 9 t ch clock high time 10 t cl clock low time 10 t is data/address/control input set-up time 10 t ih data/address/control input hold time 10 t lz data output low impedance 9 t hz t srx data output high impedance exit self refresh-to-active command 120k 120k 6 5.4 6.5 6.5 8 8 70 15 20 20 48 10 7.5 2.5 2.75 2.75 2 1 1 66 12 18 18 42 10 6 2.5 2.75 2.75 2 1 1 6 70 70 6 t wr write recovery time t ccd cas# to cas# delay time clk t mrs mode register set cycle time 2 1 2 2 1 2 e ac electrical characteristics (recommended operating conditions) 5,6,7,8 * cl is cas# latency. note: 1. stress greater than those listed under ?absolute maximum ratings?may cause permanent damage to the device. 2. all voltages are referenced to vss. 3. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tck and trc.input signals are changed one time during tck. 4. these parameters depend on the output loading.specified values are obtained with the output open. 5. power-up sequence is described in note 11. 6. a.c. test conditions 22 integrated silicon solution, inc. rev. c 07/20/11 is42s32160 c reference level of output signals 1.4v /1.4v output load reference to the under output load input signal levels 2.4v /0.4v transition time (rise and fall)of input signals 1ns reference level of input signals 1.4v 1.4v 50w output 30pf z0= 50 w lvttl a.c. test load 7. transition times are measured between vih and vil.transition(rise and fall) of input signals are in a fixed slope (1 ns). 8. t hz defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 9. if clock rising time is longer than 1 ns, (t r /2 -0.5)ns should be added to the parameter. 10. assumed input rise and fall time t t (t r &t f )= 1 ns if t r or t f is longer than 1 ns,transient time compensation should be considered,i.e.,[(tr +tf)/2 -1 ]ns should be added to the parameter. 11. power up sequence power up must be performed in the following sequence. (i) power must be applied to v dd and v ddq (simultaneously) when all input signals are held ?nop?state and both cke =?h?and dqm =?h.?the clk signals must be started at the same time (ii) after power-up,a pause of 200 m seconds minimum is required.then,it is recommended that dqm is held ?high?(v dd levels)to ensure dq output is in high impedence. (iii) all banks must be precharged. (iv) mode register set command must be asserted to initialize the mode register. (v ) a minimum of 2 auto-refresh dummy cycles must be required to stabilize the internal circuitry of the device. lvttl interface integrated silicon solution, inc. ? 1-800-379-4774 23 rev. c 07/20/11 is42s32160c i ? i timing waveforms ac parameters for write timing (burst length=4, cas# latency=2) -5 , , -7 , x x bs0,1 t ch t cl t ck2 t is t is t ih begin auto precharge bank a begin auto precharge bank b t is t ih t is rbx cax rbx cbx ray cay raz rby t rcd t dal t rc t is t ih t wr t rp t rrd ax0 ax1 ax2 ax3 bx0 bx1 bx2 bx3 ay 0 ay 1 ay 2 ay 3 activate command bank a write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write command bank a precharge command bank a activate command bank a activate command bank b clk cke cs# ras# cas# we# a ddr. dqm dq hi-z t0 t2t1 t3 t4 t5 t6 t7 t9t8 t12t11t10 t14 t13 t15 t16 t17 t18 t19 t21t20 t22 24 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c ac parameters for read timing (burst length=2, cas# latency=2) a10 add dq t ch t cl t ck2 t is t is t ih begin auto precharge bank b t ih t ih t is rax rax cax rbx rbx cbx ray ray t rrd t ras t rc t rcd t ac2 t lz t oh t hz ax0 ax1 bx0 bx1 t rp activate command bank a rea d command bank a activate command bank b read with auto precharge command bank b precharge command bank a activate command bank a hi-z t ac2 t hz t0 t2t1 t3 t4 t5 t6 t7 t9t8 t12t11t10 t13 bs0,1 clk cke cs# ras# cas# we# dqm integrated silicon solution, inc. ? 1-800-379-4774 25 rev. c 07/20/11 is42s32160c a10 add dqm dq t ck2 rax rax cax t rp t rc ax0 ax1 ax2 ax3 precharge all command auto refresh command auto refresh command activate command bank a read command bank a t rc t0 t2t1 t3 t4 t5 t6 t7 t9t8 t12t11t10 t14 t13 t15 t16 t17 t18 t19 t21t20 t22 bs0,1 clk cke cs# ras# cas# we# dq auto refresh (cbr)(burst length=4, cas# latency=2) 26 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c power on sequence and auto refresh (cbr) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs ras cas we a10 add d qm dq high level is required minimum of 2 refresh cycles are required t mrs t rp high level is necessary t rc address key inputs be stable for 200us precharge all banks must command 1st auto command refresh 2nd auto refresh command mode set command command register hi-z b s0, 1 integrated silicon solution, inc. ? 1-800-379-4774 27 rev. c 07/20/11 is42s32160c i ? i self refresh entry & exit cycle note:to enter selfrefresh mode 1. cs#,ras#&cas#with cke should be low at the same clock cycle. 2. after 1 clock cycle,all the inputs including the system clock can be don ?t care except for cke. 3. the device remains in selfrefresh mode as long as cke stays ?low?. once the device enters selfrefresh mode,minimum tras is required before exit from selfrefresh. to exit selfrefresh mode 1. system clock restart and be stable before returning cke high. 2. enable cke and cke should be set high for minimum time of tsrx. 3. cs#starts from high. 4. minimum trc is required after cke going high to complete selfrefresh exit. 5. 8192 cycles of burst autorefresh is required before selfrefresh entry and after selfrefresh exit if the system uses burst refresh. clk cke cs# ras# cas# bs0,1 add we# dqm dq *note 1 *note 2 t is *note 3 *note 4 t rc(min) *note 7 *note 5 *note 6 *note 8 *note 8 hi-z hi-z selfrefresh enter selfrefresh exit auto refresh t srx t pde t0 t2t1 t3 t4 t5 t6 t7 t9t8 t12t11t10 t14 t13 t15 t16 t17 t18 t19 28 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c clock suspension during burst read (using cke) (burst length=4, cas# latency=2) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 t ck2 rax rax cax hi-z ax0 ax1 ax2 ax3 activate command bank a rea d command bank a clock suspend 1 cycle t hz clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq clock suspend 2 cycle clock suspend 3 cycle note: cke to clk disable/enable =1 clock integrated silicon solution, inc. ? 1-800-379-4774 29 rev. c 07/22/11 is42s32160c i ? i clock suspension during burst read (using cke) (burst length=4, cas# latency=3) ( note: cke to clk disable/enable =1 clock t0t 1 t3t4t5t6t7t8t9t10t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 t ck3 rax rax cax hi-z ax0 ax1 ax2 ax3 t hz t 2 clock suspend 1 cycle clock suspend 2 cycle clock suspend 3 cycle activate command bank a rea d command bank a clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z 30 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21 t2 2 t ck2 rax rax cax dax0 dax1 dax2 dax3 clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z activate command bank a write command bank a clock suspend 1 cycle clock suspend 2 cycle clock suspend 3 cycle clock suspension during burst write (using cke) (burst length=4, cas# latency=2) ( note: cke to clk disable/enable =1 clock integrated silicon solution, inc. ? 1-800-379-4774 31 rev. c 07/20/11 is42s32160c i ? i clock suspension during burst write (using cke) (burst length=4, cas# latency=3) ( note: cke to clk disable/enable =1 clock t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 dax0 dax1 dax2 dax 3 t ck3 rax rax cax clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z activate command bank a clock suspend 1 cycle clock suspend 2 cycle clock suspend 3 cycle write command bank a 32 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21t2 2 t ck2 t is t pde rax rax cax t hz ax3 ax2 ax1 ax0 power down mode entry power down mode entry mode exit clock mask start standby any valid active standby clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z activate command bank a rea d command bank a power down mode exit power down clock mask end precharge command bank a precharge command power down mode and clock mask (burst length=4, cas# latency=2) integrated silicon solution, inc. ? 1-800-379-4774 33 rev. c 07/20/11 is42s32160c random column read (page within same bank) (burst length=4, cas# latency=2) t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21t22 t ck2 aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 raw raw caw cax cay caz az0 az1 az2 az3 activate raz raz clk cke cs# ras# cas# we# ba0,1 a10 add dqm dq hi-z activate command bank a rea d command bank a precharge command bank a rea d command bank a command bank a rea d command bank a rea d command bank a 34 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c random column read (page within same bank) (burst length=4, cas# latency=3) t0t 1t2t3t4t5t6t7t8t9t10t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 t ck3 aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 raw raw caw cax cay caz raz raz az0 clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z activate command bank a activate command bank a rea d command bank a rea d command bank a rea d command bank a rea d command bank a precharge command bank a integrated silicon solution, inc. ? 1-800-379-4774 35 rev. c 07/20/11 is42s32160c random column write (page within same bank) (burst length=4, cas# latency=2) t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21t2 2 t ck2 dbw0 dbx0 dbx1 dby0 rbw cbw cbx cb y cb z rbz rb z rbw dbw1 dbw2 dbw3 dby1 dby2 dby3 dbz0 dbz1 dbz2 dbz3 clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z write command bank a write command bank b write command bank b write command bank b activate command bank a activate command bank b precharge command bank b 36 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c random column write (page within same bank) (burst length=4, cas# latency=3) t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21t2 2 t ck3 dbw0 dbx0 dbx1 rbw cbw cbx cby cbz dbz0 rbz rbz rbw dbz1 dbz2 dbw1 dbw2 dbw3 dby0 dby1 dby2 dby3 clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z write command bank a write command bank b write command bank b write command bank b activate command bank a activate command bank b precharge command bank b integrated silicon solution, inc. ? 1-800-379-4774 37 rev. c 07/20/11 is42s32160c random row read (interleaving banks) (burst length=8, cas# latency=3) t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21t2 2 t ck3 bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 rbx rbx rby cby high rax ax7 by0 ax2 ax3 ax4 ax5 ax6 cbx cax rax rby t rcd t ac3 t rp clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z activate command bank a rea d command bank a precharge command bank a activate command bank b activate command bank b rea d command bank b rea d command bank b precharge command bank b 38 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 t ck2 dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 rax rax ray cay rbx dbx7 dbx2 dbx3 dbx4 dbx5 dbx6 cax cbx rbx ray t rcd day3 day0 day1 day2 day4 t wr* t rp t wr* * t wr > t wr (min.) clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z write command bank a write command bank a activate command bank a activate command bank a precharge command bank a write command bank b activate command bank b precharge command bank b high random row write (interleaving banks) (burst length=8, cas# latency=2) integrated silicon solution, inc. ? 1-800-379-4774 39 rev. c 07/20/11 is42s32160c random row write (interleaving banks) (burst length=8, cas# latency=3) t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21t2 2 t ck3 dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 rax rax ray cay rbx dbx7 dbx2 dbx3 dbx4 dbx5 dbx6 cax cbx rbx ray t rcd day3 day0 day1 day2 t wr* t rp t wr* * t wr > t wr (min.) clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z write command bank a write command bank a activate command bank a activate command bank a precharge command bank a write command bank b activate command bank b precharge command bank b high 38 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 t ck2 dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 rax rax ray cay rbx dbx7 dbx2 dbx3 dbx4 dbx5 dbx6 cax cbx rbx ray t rcd day3 day0 day1 day2 day4 t wr* t rp t wr* * t wr > t wr (min.) clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z write command bank a write command bank a activate command bank a activate command bank a precharge command bank a write command bank b activate command bank b precharge command bank b high random row write (interleaving banks) (burst length=8, cas# latency=2) integrated silicon solution, inc. ? 1-800-379-4774 41 rev. c 07/20/11 is42s32160c read and write cycle (burst length=4, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 t ck3 ax0 ax1 ax2 ax3 day0 day1 az3 day3 az0 az1 rax rax cax cay caz clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z write command bank a activate command bank a rea d command bank a rea d command bank a the write data is masked with a zero clock latency the read data is masked with a two clock latency 42 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 t ck2 bw0 bw1 bx0 bx1 by1 ay0 bz0 rax rax ax0 ax1 ax2 ax3 by0 ay1 bz1 bz2 bz3 t rcd t ac2 cay rax rax cbw cbx cby cay cbz clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z activate command bank a rea d command bank a rea d command bank a precharge command bank a activate command bank b rea d command bank b rea d command bank b rea d command bank b rea d command bank b precharge command bank b interleaving column read cycle (burst length=4, cas# latency=2) integrated silicon solution, inc. ? 1-800-379-4774 43 rev. c 07/20/11 is42s32160c t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 t ck3 bx0 bx1 by0 by1 bz1 a y0 ay 2 rax rax ax0 ax1 ax2 ax3 bz0 ay1 ay 3 t rcd t ac3 cax rbx rbx cbx cby cbz cay clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z activate command bank a rea d command bank a rea d command bank a precharge command bank a activate command bank b rea d command bank b rea d command bank b rea d command bank b precharge command bank b interleaved column read cycle (burst length=4, cas# latency=3) 44 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t ck2 dbx0 dbx1 day0 rax rax dax0 dax1 dax2 dax3 day1 t rcd cax rbw rbw cbw cbx cby cay t rrd t rp t wr t rp cbz dbz0 dbz1 dbz2 dbz3 dby0 dby1 dbw0 dbw1 clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z write command bank a write command bank a activate command bank a precharge command bank a write command bank b write command bank b write command bank b write command bank b activate command bank b precharge command bank b interleaved column write cycle (burst length=4, cas# latency=2) integrated silicon solution, inc. ? 1-800-379-4774 45 rev. c 07/20/11 is42s32160c interleaved column write cycle (burst length=4, cas# latency=3) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t ck3 dbw0 dbw1 dbx0 dbx1 dby1 day0 rax rax dax0 dax1 dax2 dax3 dby0 day1 t rcd cax rbw rbw cbw cbx cby cay t rrd > t rrd(min) t rp t wr t wr(min) cbz dbz0 dbz1 dbz2 dbz3 clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z write command bank a write command bank a activate command bank a precharge command bank a write command bank b write command bank b write command bank b write command bank b activate command bank b precharge command bank b 46 integrated silicon solution, inc. rev. c 07/22/11 is42s32160c auto precharge after read burst (burst length=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 t ck2 bx0 bx1 bx2 bx3 ay1 ay2 rax rax rbx ax0 ax1 ax2 ax3 ay0 ay3 by0 rbx cbx rby ray cby by1 by2 by3 az0 az1 az2 cax rby raz caz raz clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z activate command bank a activate command bank a rea d command bank a activate command bank b activate command bank b high read with auto precharge command bank b read with auto precharge command bank b read with auto precharge command bank a read with auto precharge command bank a integrated silicon solution, inc. ? 1-800-379-4774 47 rev. c 07/20/11 is42s32160c auto precharge after read burst (burst length=4, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t ck3 bx0 bx1 bx2 bx3 ay1 ay2 rax rax rbx ax0 ax1 ax2 ax3 ay0 ay3 by0 rbx cbx by1 by2 by3 cax rby cby rby ca y clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z activate command bank a rea d command bank a activate command bank b activate command bank b high read with auto precharge command bank b read with auto precharge command bank b read with auto precharge command bank a 48 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c auto precharge after write burst (burst length=4, cas# latency=2) t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21t22 t ck2 dbx0 dbx1 dbx2 dbx3 day1 day2 rax rax rbx dax0 dax1 dax2 dax3 day0 day3 cbx cay rby cby rby daz0 daz1 daz2 daz3 cax rbx caz raz raz dby0 dby1 dby2 dby3 clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z write command bank a activate command bank a activate command bank a activate command bank b activate command bank b high write with auto precharge command bank b write with auto precharge command bank b write with auto precharge command bank a write with auto precharge command bank a integrated silicon solution, inc. ? 1-800-379-4774 49 rev. c 07/21/11 is42s32160c auto precharge after write burst (burst length=4, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 t ck3 dbx0 dbx1 dbx2 dbx3 day1 day2 rax rax rbx dax0 dax1 dax2 dax3 day0 day3 cbx cay cax rbx cby rby rby ? dby0 dby1 dby2 dby3 clk cke cs# ras# cas# we# bs0,1 a9 add dqm dq hi-z write command bank a activate command bank a activate command bank b activate command bank b high write with auto precharge command bank b write with auto precharge command bank b write with auto precharge command bank a 50 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c full page read cycle (burst length=full page, cas# latency=2) t0 t 1t2t3t4t5t6t7t8t9t10t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 ax ax+1 bx bx+1 bx+3 bx+4 rax rax ax+1 ax+2 ax-2 ax- 1 b x+2 bx+5 cbx rbx cax rby rby ax bx+6 t ck2 t rp rbx clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z activate command bank a activate command bank b activate command bank b precharge command bank b high burst stop command the burst counter wraps from the highest order page address back to zero during this time interval rea d command bank a rea d command bank b full page burst operation does not term in ate when the burst length is sat is fied; the burst counter incre ments and continues bursting beginning with the starting address. integrated silicon solution, inc. ? 1-800-379-4774 51 rev. c 07/20/11 is42s32160c full page read cycle (burst length=full page, cas# latency=3) t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21t2 2 bx bx+1 rax rax ax+1 ax-2 ax-1 cbx rbx cax rby rby ax t ck3 t rp rbx ax+2 ax ax+1 bx+2 bx+3 bx+4 bx+5 clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z activate command bank a activate command bank b activate command bank b precharge command bank b high burst stop command the burst counter wraps from the highest order page address back to zero during this time interval rea d command bank a rea d command bank b full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. 52 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c full page write cycle (burst length=full page, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 rax rax cbx rbx cax rby rby t ck2 5 rbx dax dax+1 dax+2 dax+3 dax-1 dax dax+1 dbx dbx+1 dbx+2 dbx+3 dbx+4 dbx+5 dbx+6 clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z write command bank a activate command bank a write command bank b activate command bank b activate command bank b precharge command bank b high burst stop command data is ignored full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. the burst counter wraps from the highest order page address back to zero during this time interval integrated silicon solution, inc. ? 1-800-379-4774 53 rev. c 07/20/11 is42s32160c full page write cycle (burst length=full page, cas# latency=3) t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21t2 2 rax rax cbx rbx cax rby rby t ck3 rbx data is ignor ed dax dax+1 dax+2 dax+3 dax-1 dax dax+1 dbx dbx+1 dbx+3 dbx+4 dbx+5 clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq hi-z high write command bank a activate command bank a write command bank b activate command bank b the burst counter wraps from the highes t order page address back to zero during this time interval activate command bank b precharge command bank b burst stop command full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. 54 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c byte write operation (burst length=4, cas# latency=2) t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21t22 rax rax cay cax t ck2 caz ax0 ax1 ax2 ax1 ax2 ax3 day1 day2 day0 day1 day3 az1 az2 az1 az2 az3 write command bank a clk cke cs# ras# cas# we# bs0,1 a10 add high activate command bank a command bank a dqm0 dqm1,2,3 dq0 - dq7 dq8 - dq15 rea d command bank a rea d are masked upper 3 bytes are masked upper 3 bytes lower byte is masked lower byte is masked lower byte is masked integrated silicon solution, inc. ? 1-800-379-4774 55 rev. c 07/20/11 is42s32160c full page random column read (burst length=full page, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 t ck2 ax0 bx0 ay0 ay1 by0 by1 az0 az1 az2 bz0 bz1 bz2 t rp t rrd t rcd rax rax rbx rbx cax cbx cay cby caz cbz rbw rbw clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq command bank b activate command bank a activate command bank b activate command bank b rea d command bank b rea d command bank b rea d command bank a rea d command bank a rea d command bank a rea d precharge command bank b (precharge temination) 56 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c full page random column write (burst length=full page, cas# latency=2) t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21t2 2 t ck2 dax0 dbx0 day0 day1 dby0 dby1 daz0 daz1 daz2 dbz0 t rp t rrd t rcd rax rax rbx rbx cax cbx cay cby caz cbz rbw rbw t wr dbz1 dbz2 clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq write command bank a write command bank a write command bank a activate command bank a write command bank b write command bank b write command bank b activate command bank b activate command bank b precharge command bank b (precharge temination) write data is masked integrated silicon solution, inc. ? 1-800-379-4774 57 rev. c 07/20/11 is42s32160c precharge termination of a burst (burst length=8 or full page, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t2 2 t ck2 dax0 dax1 dax2 dax3 ay2 ay0 ay1 rax rax ray cax ray cay az0 az1 az2 t wr t rp t rp raz caz t rp raz clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq high write command bank a activate command bank a activate command bank a activate command bank a command bank a precharge command bank a precharge command bank a precharge command bank a read command bank a read precharge termination of a write burst. precharge termination of a read burst. write data is masked. 58 integrated silicon solution, inc. rev. c 07/20/11 is42s32160c precharge termination of a burst (burst length=4,8 or full page, cas# latency=3) t0t 1t2t3t4t5t6t7t8t9t10t 11t12t13t14t15t16t17t18t19t20t21t2 2 t ck3 dax0 ay0 ay1 ay2 rax rax ray cax ray cay t wr t rp t rp raz raz dax1 clk cke cs# ras# cas# we# bs0,1 a10 add dqm dq high write command bank a command bank a activate command bank a activate command bank a activate command bank a precharge command bank a precharge command bank a write data is masked precharge termination of a write burst precharge termination of a read burst read integrated silicon solution, inc. 59 rev. c 07/20/11 is42s32160c ordering information - v d d = 3.3v commercial range: 0 c to 70c frequency speed (ns) order part no. package 133 mhz 7.5 is42s32160c-75bl 8x13mm bga, lead-free 166 mhz 6.0 IS42S32160C-6BL 8x13mm bga, lead-free industrial range: -40 c to 85c frequency speed (ns) order part no. package 133 mhz 7.5 is42s32160c-75bli 8x13mm bga, lead-free 166 mhz 6.0 is42s32160c-6bi 8x13mm bga 166 mhz 6.0 IS42S32160C-6BLi 8x13mm bga, lead-free 2. reference document : jedec ms-207 1. controlling dimension : mm . note : 08/28/2008 package outline |
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